Functional Coverage Analysis of Ovm Based Verification of H.264 Cavld Slice Header Decoder

Commercial chip design verification is a complex activity involving many abstraction levels (such as architectural, register transfer, gate, switch, circuit, fabrication), many different aspects of design (such as timing, speed, functional, power, reliability and manufacturability) and many different design styles (such as ASIC, full custom, semi-custom, memory, cores, and asynchronous). In this paper, functional coverage analysis of verification of RTL (Register Transfer Level) design of H.264 CAVLD (context-based adaptive variable length decoding) slice header decoder using SystemVerilog implementation of OVM (open verification methodology) is presented. The methodology used for verification is OVM which has gathered very positive press coverage, including awards from magazines and industry organizations. There is no doubt that the OVM is one of the biggest stories in recent EDA (electronic design automation) history. The SystemVerilog language is at the heart of the OVM which inherited features from Verilog HDL, VHDL, C, C++ and adopted by IEEE as hardware description and verification language in 2005. The verification environment developed in OVM provides multiple levels of reuse, both within projects and between projects. Emphasis is put onto the actual usage of the verification components and functional coverage. The whole verification is done using SystemVerilog hardware description and verification language. We are using QuestaSim 6.6b for simulation.